There are multiple types of memory devices. Amongst them include static random access memory (SRAM) devices. Generally, SRAMs are implemented within microprocessor devices, microcontroller devices or other processing devices, for example as internal caches. SRAMs may differ from dynamic random access memory (DRAM) devices in at least one particular feature, which is periodic refresh, as in the SRAMs do not require periodic refresh of data bits stored in their memory cells.
There are different types of SRAM memory cell designs. The most commonly available SRAM memory cell design includes six transistors (i.e., a 6T SRAM cell), of which two n-channel metal oxide semiconductor (NMOS) transistors and two p-channel metal oxide semiconductor (PMOS) transistors form a cross-coupled inverter with two additional NMOS transistors forming pass gates to the respective terminals of the cross-coupled inverters. The 6T SRAM cell generally occupies a small area on the semiconductor substrate. Therefore, the 6T SRAM cell is generally preferred when area on a semiconductor substrate may be limited. However, 6T SRAM cells may have poor noise margin, which may adversely affect the performance of SRAM devices.
As an alternative, eight-transistor SRAM structures (commonly referred to as 8T SRAM cells) may be used in place of 6T SRAM cells. Compared to 6T SRAM cells, 8T SRAM cells have better noise margin. However, the 8T SRAM structure requires a relatively large silicon substrate area. In addition to that, the 8T SRAM cell, which is predominantly formed using NMOS transistors, may not satisfy the p-type diffusion requirement on the silicon substrate.